ECET 230 ECET230 ECET/230 Week 4

ECET 230 ECET230 ECET/230 Week 4

1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW.

2. Sketch the Q output for the waveforms shown. Assume that Q starts LOW.

3. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

4. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

5. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

6. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

7. Sketch the Q output for the circuit shown below. Assume that Q starts LOW.

8. Using Quartus II, or an equivalent VHDL entry program, model the D flip-flop shown below. Attach the simulation file.

9. Using Quartus II, or an equivalent VHDL entry program, model the J-K flip-flop shown below. Attach the simulation file.