ECET 230 ECET230 ECET/230 Week 5

ECET 230 ECET230 ECET/230 Week 5

1.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the circuit below. Attach the .vhd and simulation files.

2.What is the output frequency of Q1 in the circuit shown below?

3.A synchronous binary counter is used to divide a 1 MHz input frequency to 3.90625 kHz. What is the MOD number of the counter and how many flip-flops are required?

4. If the MOD-8 binary counter is driven by a 10 MHz input clock with a 5% duty cycle, what is the output frequency and duty cycle of the final stage?

5.Determine the output frequency for the cascaded counter configuration shown below.

6.Determine the count sequence for the counter shown below.

7. Write the VHDL text file for a MOD-1024 counter using INTEGER types

8.Develop the state diagram for a MOD-5 counter with the following count sequence:
000, 001, 010, 110, 111, 000, etc. All undefined states must return to 000.